1. Field of the Invention
The present invention relates to the field of memories and more particularly to dynamic random access memories (DRAM).
2. Description of the Related Art
Dynamic DRAM memories are very popular because of their large storage capacity. On the other hand, they require periodic refresh and, furthermore access to DRAM is much slower than access to static memories.
There have been attempts to increase the bandwidth of dynamic memories. To this end, a known technique consists in associating to the memory plane buffers or memories controlled by an adapted memory controller.
U.S. Pat. No. 6,675,256 entitled “Fast DRAM Control Method and Adapted Controller” by M. Harrand, describes a method and a memory controller for controlling a dynamic memory comprising a memory plane made up of a memory cell array and at least two buffers.
U.S. Pat. No. 6,631,441 by M. Harrand and D. Doise, describes a fast DRAM memory structure comprising a memory plane associated with at least two buffers for accessing the memory plane and for reading or writing the memory.
U.S. Published Patent Application No. 2005/0185492 entitled “Dynamic Random Access Memory Having at Least Two Buffer Registers and Method for Controlling Such a Memory”, filed Dec. 21, 2004 by the owner of this application, teaches how to add an error correcting system that is absolutely transparent for the user. In particular, a continuous data stream is maintained even when writing words, or parts of a word, that are shorter than the data set to which the error correcting code is applied.
Thus, this error correcting system makes it possible to significantly improve reliability of the memory and makes it less sensitive to electromagnetic disturbances that are sources of error. Reliability improvement is such, that this technique can even be considered as an alternative to expensive burn-in methods, in particular thermal ones.
The architecture described in U.S. Published Patent Application No. 2005/0185492 allows to increase bandwidth only when burst-accessing memory within a single page of data read in the memory matrix. An uninterrupted data stream on the data bus is then obtained, thus allowing an optimal bandwidth.
On the other hand, when accessing the memory successively at different pages, the data stream is stopped, thus slowing down memory performances.